From 47796aeb825b54c442c6e6fcb65a9e0e77b7b0d9 Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Fri, 4 Apr 2025 09:27:45 -0700 Subject: [PATCH 2/3] Add support for PCA9555 PCA9555 is quite similar to PCA9554, only it supports 16 GPIO pins instead of 8. Signed-off-by: Guenter Roeck --- hw/gpio/Kconfig | 4 + hw/gpio/meson.build | 1 + hw/gpio/pca9555.c | 338 +++++++++++++++++++++++++++++++++ include/hw/gpio/pca9555.h | 36 ++++ include/hw/gpio/pca9555_regs.h | 19 ++ 5 files changed, 398 insertions(+) create mode 100644 hw/gpio/pca9555.c create mode 100644 include/hw/gpio/pca9555.h create mode 100644 include/hw/gpio/pca9555_regs.h diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig index a209294c20..b939e1482d 100644 --- a/hw/gpio/Kconfig +++ b/hw/gpio/Kconfig @@ -24,6 +24,10 @@ config PCA9554 bool depends on I2C +config PCA9555 + bool + depends on I2C + config PCF8574 bool depends on I2C diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 74840619c0..cd24678e6e 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -3,6 +3,7 @@ system_ss.add(when: 'CONFIG_GPIO_MPC8XXX', if_true: files('mpc8xxx.c')) system_ss.add(when: 'CONFIG_GPIO_PWR', if_true: files('gpio_pwr.c')) system_ss.add(when: 'CONFIG_PCA9552', if_true: files('pca9552.c')) system_ss.add(when: 'CONFIG_PCA9554', if_true: files('pca9554.c')) +system_ss.add(when: 'CONFIG_PCA9555', if_true: files('pca9555.c')) system_ss.add(when: 'CONFIG_PL061', if_true: files('pl061.c')) system_ss.add(when: 'CONFIG_ZAURUS_SCOOP', if_true: files('zaurus.c')) diff --git a/hw/gpio/pca9555.c b/hw/gpio/pca9555.c new file mode 100644 index 0000000000..911941ec61 --- /dev/null +++ b/hw/gpio/pca9555.c @@ -0,0 +1,338 @@ +/* + * PCA9555 I/O port + * + * Derived from pca9554.c. + * Copyright (c) 2023, IBM Corporation. + * + * Copyright (c) 2023, IBM Corporation. + * + * PCA9554 and PCA9555 are quite similar. The main difference is that + * PCA9554 supports 8 pins while PCA9555 supports 16 pins. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/bitops.h" +#include "hw/qdev-properties.h" +#include "hw/gpio/pca9555.h" +#include "hw/gpio/pca9555_regs.h" +#include "hw/irq.h" +#include "migration/vmstate.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "trace.h" +#include "qom/object.h" + +struct PCA9555Class { + /*< private >*/ + I2CSlaveClass parent_class; + /*< public >*/ +}; +typedef struct PCA9555Class PCA9555Class; + +DECLARE_CLASS_CHECKERS(PCA9555Class, PCA9555, + TYPE_PCA9555) + +#define PCA9555_PIN_LOW 0x0 +#define PCA9555_PIN_HIZ 0x1 + +static const char *pin_state[] = {"low", "high"}; + +static void pca9555_update_pin_input(PCA9555State *s) +{ + int i; + uint16_t config = s->regs[PCA9555_CONFIG]; + uint16_t output = s->regs[PCA9555_OUTPUT]; + uint16_t internal_state = config | output; + + for (i = 0; i < PCA9555_PIN_COUNT; i++) { + uint16_t bit_mask = 1 << i; + uint16_t internal_pin_state = (internal_state >> i) & 0x1; + uint16_t old_value = s->regs[PCA9555_INPUT] & bit_mask; + uint16_t new_value; + + switch (internal_pin_state) { + case PCA9555_PIN_LOW: + s->regs[PCA9555_INPUT] &= ~bit_mask; + break; + case PCA9555_PIN_HIZ: + /* + * pullup sets it to a logical 1 unless + * external device drives it low. + */ + if (s->ext_state[i] == PCA9555_PIN_LOW) { + s->regs[PCA9555_INPUT] &= ~bit_mask; + } else { + s->regs[PCA9555_INPUT] |= bit_mask; + } + break; + default: + break; + } + + /* update irq state only if pin state changed */ + new_value = s->regs[PCA9555_INPUT] & bit_mask; + if (new_value != old_value) { + if (new_value) { + /* changed from 0 to 1 */ + qemu_set_irq(s->gpio_out[i], 1); + } else { + /* changed from 1 to 0 */ + qemu_set_irq(s->gpio_out[i], 0); + } + } + } +} + +static uint8_t pca9555_read(PCA9555State *s, uint8_t _reg) +{ + int shift = (_reg & 1) * 8; + uint8_t reg = _reg >> 1; + + switch (reg) { + case PCA9555_INPUT: + return ((s->regs[reg] ^ s->regs[PCA9555_POLARITY]) >> shift) & 0xff; + case PCA9555_OUTPUT: + case PCA9555_POLARITY: + case PCA9555_CONFIG: + return (s->regs[reg] >> shift) & 0xff; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: unexpected read from register %d\n", + __func__, reg); + return 0xff; + } +} + +static void pca9555_write(PCA9555State *s, uint8_t _reg, uint8_t data) +{ + int shift = (_reg & 1) * 8; + int mask = 0xff << shift; + uint8_t reg = _reg >> 1; + + switch (reg) { + case PCA9555_OUTPUT: + case PCA9555_CONFIG: + s->regs[reg] = (s->regs[reg] & ~mask) | (data << shift); + pca9555_update_pin_input(s); + break; + case PCA9555_POLARITY: + s->regs[reg] = (s->regs[reg] & ~mask) | (data << shift); + break; + case PCA9555_INPUT: + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: unexpected write to register %d\n", + __func__, _reg); + } +} + +static uint8_t pca9555_recv(I2CSlave *i2c) +{ + PCA9555State *s = PCA9555(i2c); + uint8_t ret; + + ret = pca9555_read(s, s->pointer & 0x7); + + return ret; +} + +static int pca9555_send(I2CSlave *i2c, uint8_t data) +{ + PCA9555State *s = PCA9555(i2c); + + /* First byte sent by is the register address */ + if (s->len == 0) { + s->pointer = data; + s->len++; + } else { + pca9555_write(s, s->pointer & 0x7, data); + } + + return 0; +} + +static int pca9555_event(I2CSlave *i2c, enum i2c_event event) +{ + PCA9555State *s = PCA9555(i2c); + + s->len = 0; + return 0; +} + +static void pca9555_get_pin(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + PCA9555State *s = PCA9555(obj); + int pin, rc; + uint16_t state; + + rc = sscanf(name, "pin%2d", &pin); + if (rc != 1) { + error_setg(errp, "%s: error reading %s", __func__, name); + return; + } + if (pin < 0 || pin >= PCA9555_PIN_COUNT) { + error_setg(errp, "%s invalid pin %s", __func__, name); + return; + } + + state = s->regs[PCA9555_CONFIG]; + state |= s->regs[PCA9555_OUTPUT]; + state = (state >> pin) & 0x1; + visit_type_str(v, name, (char **)&pin_state[state], errp); +} + +static void pca9555_set_pin(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + PCA9555State *s = PCA9555(obj); + int pin, rc; + uint16_t state, mask; + char *state_str; + + if (!visit_type_str(v, name, &state_str, errp)) { + return; + } + rc = sscanf(name, "pin%2d", &pin); + if (rc != 1) { + error_setg(errp, "%s: error reading %s", __func__, name); + return; + } + if (pin < 0 || pin >= PCA9555_PIN_COUNT) { + error_setg(errp, "%s invalid pin %s", __func__, name); + return; + } + + for (state = 0; state < ARRAY_SIZE(pin_state); state++) { + if (!strcmp(state_str, pin_state[state])) { + break; + } + } + if (state >= ARRAY_SIZE(pin_state)) { + error_setg(errp, "%s invalid pin state %s", __func__, state_str); + return; + } + + /* First, modify the output register bit */ + mask = 0x1 << pin; + if (state == PCA9555_PIN_LOW) { + s->regs[PCA9555_OUTPUT] &= ~mask; + } else { + s->regs[PCA9555_OUTPUT] |= mask; + } + + /* Then, clear the config register bit for output mode */ + s->regs[PCA9555_CONFIG] &= ~mask; + + pca9555_update_pin_input(s); +} + +static const VMStateDescription pca9555_vmstate = { + .name = "PCA9555", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_UINT8(len, PCA9555State), + VMSTATE_UINT8(pointer, PCA9555State), + VMSTATE_UINT16_ARRAY(regs, PCA9555State, PCA9555_NR_REGS), + VMSTATE_UINT8_ARRAY(ext_state, PCA9555State, PCA9555_PIN_COUNT), + VMSTATE_I2C_SLAVE(i2c, PCA9555State), + VMSTATE_END_OF_LIST() + } +}; + +static void pca9555_reset(DeviceState *dev) +{ + PCA9555State *s = PCA9555(dev); + + s->regs[PCA9555_INPUT] = 0xFFFF; + s->regs[PCA9555_OUTPUT] = 0xFFFF; + s->regs[PCA9555_POLARITY] = 0x0; /* No pins are inverted */ + s->regs[PCA9555_CONFIG] = 0xFFFF; /* All pins are inputs */ + + memset(s->ext_state, PCA9555_PIN_HIZ, PCA9555_PIN_COUNT); + pca9555_update_pin_input(s); + + s->pointer = 0x0; + s->len = 0; +} + +static void pca9555_initfn(Object *obj) +{ + int pin; + + for (pin = 0; pin < PCA9555_PIN_COUNT; pin++) { + char *name; + + name = g_strdup_printf("pin%d", pin); + object_property_add(obj, name, "bool", pca9555_get_pin, pca9555_set_pin, + NULL, NULL); + g_free(name); + } +} + +static void pca9555_set_ext_state(PCA9555State *s, int pin, int level) +{ + if (s->ext_state[pin] != level) { + s->ext_state[pin] = level; + pca9555_update_pin_input(s); + } +} + +static void pca9555_gpio_in_handler(void *opaque, int pin, int level) +{ + + PCA9555State *s = PCA9555(opaque); + + assert((pin >= 0) && (pin < PCA9555_PIN_COUNT)); + pca9555_set_ext_state(s, pin, level); +} + +static void pca9555_realize(DeviceState *dev, Error **errp) +{ + PCA9555State *s = PCA9555(dev); + + if (!s->description) { + s->description = g_strdup("pca9555"); + } + + qdev_init_gpio_out(dev, s->gpio_out, PCA9555_PIN_COUNT); + qdev_init_gpio_in(dev, pca9555_gpio_in_handler, PCA9555_PIN_COUNT); +} + +static const Property pca9555_properties[] = { + DEFINE_PROP_STRING("description", PCA9555State, description), +}; + +static void pca9555_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); + + k->event = pca9555_event; + k->recv = pca9555_recv; + k->send = pca9555_send; + dc->realize = pca9555_realize; + device_class_set_legacy_reset(dc, pca9555_reset); + dc->vmsd = &pca9555_vmstate; + device_class_set_props(dc, pca9555_properties); +} + +static const TypeInfo pca9555_info = { + .name = TYPE_PCA9555, + .parent = TYPE_I2C_SLAVE, + .instance_init = pca9555_initfn, + .instance_size = sizeof(PCA9555State), + .class_init = pca9555_class_init, + .class_size = sizeof(PCA9555Class), + .abstract = false, +}; + +static void pca9555_register_types(void) +{ + type_register_static(&pca9555_info); +} + +type_init(pca9555_register_types) diff --git a/include/hw/gpio/pca9555.h b/include/hw/gpio/pca9555.h new file mode 100644 index 0000000000..354bcc59ee --- /dev/null +++ b/include/hw/gpio/pca9555.h @@ -0,0 +1,36 @@ +/* + * PCA9555 I/O port + * + * Copyright (c) 2023, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef PCA9555_H +#define PCA9555_H + +#include "hw/i2c/i2c.h" +#include "qom/object.h" + +#define TYPE_PCA9555 "pca9555" +typedef struct PCA9555State PCA9555State; +DECLARE_INSTANCE_CHECKER(PCA9555State, PCA9555, + TYPE_PCA9555) + +#define PCA9555_NR_REGS 4 +#define PCA9555_PIN_COUNT 16 + +struct PCA9555State { + /*< private >*/ + I2CSlave i2c; + /*< public >*/ + + uint8_t len; + uint8_t pointer; + + uint16_t regs[PCA9555_NR_REGS]; + qemu_irq gpio_out[PCA9555_PIN_COUNT]; + uint8_t ext_state[PCA9555_PIN_COUNT]; + char *description; /* For debugging purpose only */ +}; + +#endif diff --git a/include/hw/gpio/pca9555_regs.h b/include/hw/gpio/pca9555_regs.h new file mode 100644 index 0000000000..d1eb4703cf --- /dev/null +++ b/include/hw/gpio/pca9555_regs.h @@ -0,0 +1,19 @@ +/* + * PCA9554 I/O port registers + * + * Copyright (c) 2023, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef PCA9555_REGS_H +#define PCA9555_REGS_H + +/* + * Bits [0:1] are used to address a specific register. + */ +#define PCA9555_INPUT 0 /* read only input register */ +#define PCA9555_OUTPUT 1 /* read/write pin output state */ +#define PCA9555_POLARITY 2 /* Set polarity of input register */ +#define PCA9555_CONFIG 3 /* Set pins as inputs our ouputs */ + +#endif -- 2.45.2